Reference is made to FIG. 1 showing a top plan view of a semiconductor wafer 10 including a plurality of integrated circuit die 12 arranged in a matrix or array format. For tracking and quality control purposes, each wafer 10 is assigned a wafer identification (wafer_id) and that identification is typically etched into the top surface of the wafer at a location devoid of integrated circuit die 12 (for example, at or near a peripheral edge of the wafer). The wafer_id provides information specific to the wafer and/or the lot from which the wafer is obtained. For similar tracking and quality control purposes, each individual integrated circuit die 12 is also assigned a die identification (die_id). The die_id provides information specific to the integrated circuit die 12 such as its location (i.e., coordinates) within the matrix or array format of the wafer 10. It is also possible for the die_id to further include wafer identification information such that the die_id provides information as to both the identification of the wafer 10 and the location within that wafer 10 from which the integrated circuit die 12 was obtained.
The prior art teaches a number of ways for including the die_id within each integrated circuit die 12. For example, the die_id may be micro-etched in a layer of the integrated circuit die 12 (FIG. 2A) separate from any included integrated functional circuitry 16. Alternatively, the die_id may be stored in an electrically-readable non-volatile memory (NVM) circuit (FIG. 2B) within the integrated functional circuitry 16. A concern with prior art die identification techniques is that damage to the die may render the die_id unreadable. For example, in connection with the FIG. 2B implementation, damage to the die may damage the non-volatile memory circuit and/or related read circuitry making it impossible to recover the stored die_id.